One-instruction set computer

one-instruction set computer (OISC), sometimes called an ultimate reduced instruction set computer (URISC), is an abstract machine that uses only one instruction – obviating the need for a machine language opcode.[1][2][3] With a judicious choice for the single instruction and given infinite resources, an OISC is capable of being a universal computer in the same manner as traditional computers that have multiple instructions.[2]:55 OISCs have been recommended as aids in teaching computer architecture[1]:327[2]:2 and have been used as computational models in structural computing research.[3]

Machine architecture

In a Turing-complete model, each memory location can store an arbitrary integer, and – depending on the model there may be arbitrarily many locations. The instructions themselves reside in memory as a sequence of such integers.

There exists a class of universal computers with a single instruction based on bit manipulation such as bit copying or bit inversion. Since their memory model is finite, as is the memory structure used in real computers, those bit manipulation machines are equivalent to real computers rather than to Turing machines.[4]

Currently known OISCs can be roughly separated into three broad categories:

  • Bit-manipulating machines
  • Transport triggered architecture machines
  • Arithmetic-based Turing-complete machines

Bit-manipulating machines

Bit-manipulating machines are the simplest class.

BitBitJump

A bit copying machine, called BitBitJump, copies one bit in memory and passes the execution unconditionally to the address specified by one of the operands of the instruction. This process turns out to be capable of universal computation (i.e. being able to execute any algorithm and to interpret any other universal machine) because copying bits can conditionally modify the code that will be subsequently executed.

Toga computer

Another machine, called the Toga Computer, inverts a bit and passes the execution conditionally depending on the result of inversion. The unique instruction is TOGA(a,b) which stands for TOGgle a And branch to b if the result of the toggle operation is true.

 

Multi-bit copying machine

 

Similar to BitBitJump, a multi-bit copying machine copies several bits at the same time. The problem of computational universality is solved in this case by keeping predefined jump tables in the memory.

Transport triggered architecture

Transport triggered architecture (TTA) is a design in which computation is a side effect of data transport. Usually, some memory registers (triggering ports) within common address space perform an assigned operation when the instruction references them. For example, in an OISC using a single memory-to-memory copy instruction, this is done by triggering ports that perform arithmetic and instruction pointer jumps when written to.

Arithmetic-based Turing-complete machines

Arithmetic-based Turing-complete machines use an arithmetic operation and a conditional jump. Like the two previous universal computers, this class is also Turing-complete. The instruction operates on integers which may also be addresses in memory.

Currently there are several known OISCs of this class, based on different arithmetic operations:

  • addition (addleq, add and branch if less than or equal to zero)[5]
  • decrement (DJN, decrement and branch (jump) if nonzero)[6]
  • increment (P1eq, plus 1 and branch if equal to another value)[7]
  • subtraction (subleq, subtract and branch if less than or equal to zero)[8][9]
  • subtraction when possible (Arithmetic machine)

Instruction types

Common choices for the single instruction are:

  • Subtract and branch if less than or equal to zero
  • Subtract and branch if negative
  • Subtract if positive else branch
  • Reverse subtract and skip if borrow
  • Move (used as part of a transport triggered architecture)
  • Subtract and branch if non zero (SBNZ a, b, c, destination)
  • Cryptoleq (heterogeneous encrypted and unencrypted computation)

Only one of these instructions is used in a given implementation. Hence, there is no need for an opcode to identify which instruction to execute; the choice of instruction is inherent in the design of the machine, and an OISC is typically named after the instruction it uses (e.g., an SBN OISC,[2]:41 the SUBLEQ language,[3]:4 etc.). Each of the above instructions can be used to construct a Turing-complete OISC.

This article presents only subtraction-based instructions among those that are not transport triggered. However, it is possible to construct Turing complete machines using an instruction based on other arithmetic operations, e.g., addition. For example, one variation known as DLN (Decrement and jump if not zero) has only two operands and uses decrement as the base operation. For more information see Subleq derivative languages [1].

Subtract and branch if not equal to zero

The SBNZ a, b, c, d instruction (“subtract and branch if not equal to zero“) subtracts the contents at address a from the contents at address b, stores the result at address c, and then, if the result is not 0, transfers control to address d (if the result is equal to zero, execution proceeds to the next instruction in sequence).[3]

Subtract and branch if less than or equal to zero

The subleq instruction (“subtract and branch if less than or equal to zero“) subtracts the contents at address a from the contents at address b, stores the result at address b, and then, if the result is not positive, transfers control to address c (if the result is positive, execution proceeds to the next instruction in sequence).[3]:4–7

Pseudocode:

subleq a, b, c   ; Mem[b] = Mem[b] – Mem[a]

; if (Mem[b] ≤ 0) goto c

Conditional branching can be suppressed by setting the third operand equal to the address of the next instruction in sequence. If the third operand is not written, this suppression is implied.

A variant is also possible with two operands and an internal accumulator, where the accumulator is subtracted from the memory location specified by the first operand. The result is stored in both the accumulator and the memory location, and the second operand specifies the branch address:

subleq2 a, b     ; Mem[a] = Mem[a] – ACCUM

; ACCUM = Mem[a]

; if (Mem[a] ≤ 0) goto b

Although this uses only two (instead of three) operands per instruction, correspondingly more instructions are then needed to effect various logical operations.

Synthesized instructions

It is possible to synthesize many types of higher-order instructions using only the subleq instruction.[3]:9–10

Unconditional branch:

JMP c

subleq Z, Z, c

Addition can be performed by repeated subtraction, with no conditional branching; e.g., the following instructions result in the content at location a being added to the content at location b:

ADD a, b

subleq a, Z

subleq Z, b

subleq Z, Z

The first instruction subtracts the content at location a from the content at location Z (which is 0) and stores the result (which is the negative of the content at a) in location Z. The second instruction subtracts this result from b, storing in b this difference (which is now the sum of the contents originally at a and b); the third instruction restores the value 0 to Z.

A copy instruction can be implemented similarly; e.g., the following instructions result in the content at location b getting replaced by the content at location a, again assuming the content at location Z is maintained as 0:

MOV a, b

subleq b, b

subleq a, Z

subleq Z, b

subleq Z, Z

Any desired arithmetic test can be built. For example, a branch-if-zero condition can be assembled from the following instructions:

BEQ b, c

subleq b, Z, L1

subleq Z, Z, OUT

L1: subleq Z, Z

subleq Z, b, c

OUT: …

Subleq2 can also be used to synthesize higher-order instructions, although it generally requires more operations for a given task. For example, no fewer than 10 subleq2 instructions are required to flip all the bits in a given byte:

NOT a

subleq2 tmp          ; tmp = 0 (tmp = temporary register)

subleq2 tmp

subleq2 minus_one    ; acc = -1

subleq2 a            ; a’ = a + 1

subleq2 Z            ; Z = – a – 1

subleq2 tmp          ; tmp = a + 1

subleq2 a            ; a’ = 0

subleq2 tmp          ; load tmp into acc

subleq2 a            ; a’ = – a – 1 ( = ~a )

subleq2 Z            ; set Z back to 0

Emulation[edit]

The following program (written in pseudocode) emulates the execution of a subleq-based OISC:

int memory[], program_counter, a, b, c

program_counter = 0

while (program_counter >= 0):

a = memory[program_counter]

b = memory[program_counter+1]

c = memory[program_counter+2]

if (a < 0 or b < 0):

program_counter = -1

else:

memory[b] = memory[b] – memory[a]

if (memory[b] > 0):

program_counter += 3

else:

program_counter = c

This program assumes that memory[] is indexed by nonnegative integers. Consequently, for a subleq instruction (a, b, c), the program interprets a < 0, b < 0, or an executed branch to c < 0 as a halting condition. Similar interpreters written in a subleq-based language (i.e., self-interpreters, which may use self-modifying code as allowed by the nature of the subleq instruction) can be found in the external links below.

Compilation[edit]

There is a compiler called Higher Subleq written by Oleg Mazonka that compiles a simplified C program into subleq code.[11]

Subtract and branch if negative

The subneg instruction (“subtract and branch if negative“), also called SBN, is defined similarly to subleq:[2]:41,51–52

subneg a, b, c   ; Mem[b] = Mem[b] – Mem[a]

; if (Mem[b] < 0) goto c

Conditional branching can be suppressed by setting the third operand equal to the address of the next instruction in sequence. If the third operand is not written, this suppression is implied.

Synthesized instructions

It is possible to synthesize many types of higher-order instructions using only the subneg instruction. For simplicity, only one synthesized instruction is shown here to illustrate the difference between subleq and subneg.

Unconditional branch:[2]:88–89

JMP c

subneg POS, Z, c

c: subneg Z, Z

where Z and POS are locations previously set to contain 0 and a positive integer, respectively;

Unconditional branching is assured only if Z initially contains 0 (or a value less than the integer stored in POS). A follow-up instruction is required to clear Z after the branching, assuming that the content of Z must be maintained as 0.

subneg4

A variant is also possible with four operands – subneg4. The reversal of minuend and subtrahend eases implementation in hardware. The non-destructive result simplifies the synthetic instructions.

subneg4 s, m, r, j   ; subtrahend, minuend, result and jump addresses

; Mem[r] = Mem[m] – Mem[s]

; if (Mem[r] < 0) goto j

Arithmetic machine

In an attempt to make Turing machine more intuitive, Z. A. Melzac consider the task of computing with positive numbers. The machine has an infinite abacus, an infinite number of counters (pebbles, tally sticks) initially at a special location S. The machine is able to do one operation:

Take from location X as many counters as there are in location Y and transfer them to location Z and proceed to next instruction.

If this operation is not possible because there is not enough counters in Y, then leave the abacus as it is and proceed to instruction T.

This essentially a subneg where the test is done before rather than after the subtraction, in order to keep all numbers positive and mimic a human operator computing on a real world abacus.

Pseudocode:

command X, Y, Z, T   ; if (Mem[Y] < Mem[X]) goto T

; Mem[Z] = Mem[Y] – Mem[X]

After giving a few programs: multiplication, gcd, computing the n-th prime number, representation in base b of an arbitrary number, sorting in order of magnitude, Melzac shows explicitly how to simulate an arbitrary Turing machine on his arithmetic machine.

He mentions that it can easily be shown using the elements of recursive functions that every number calculable on the arithmetic machine is computable. A proof of which was given by Lambek[12] on an equivalent two instruction machine : X+ (increment X) and X− else T (decrement X if it not empty, else jump to T).

Reverse subtract and skip if borrow

In a reverse subtract and skip if borrow (RSSB) instruction, the accumulator is subtracted from the memory location and the next instruction is skipped if there was a borrow (memory location was smaller than the accumulator). The result is stored in both the accumulator and the memory location. The program counter is mapped to memory location 0. The accumulator is mapped to memory location 1.[2]

Example

To set x to the value of y minus z:

# First, move z to the destination location x.

RSSB temp # Three instructions required to clear acc, temp [See Note 1]

RSSB temp

RSSB temp

RSSB x    # Two instructions clear acc, x, since acc is already clear

RSSB x

RSSB y    # Load y into acc: no borrow

RSSB temp # Store -y into acc, temp: always borrow and skip

RSSB temp # Skipped

RSSB x    # Store y into x, acc

# Second, perform the operation.

RSSB temp # Three instructions required to clear acc, temp

RSSB temp

RSSB temp

RSSB z    # Load z

RSSB x    # x = y – z [See Note 2]

[Note 1] If the value stored at “temp” is initially a negative value and the instruction that executed right before the first “RSSB temp” in this routine borrowed, then four “RSSB temp” instructions will be required for the routine to work.

[Note 2] If the value stored at “z” is initially a negative value then the final “RSSB x” will be skipped and thus the routine will not work.

Transport triggered architecture

A transport triggered architecture uses only the move instruction, hence it was originally called a “move machine”. This instruction moves the contents of one memory location to another memory location combining with the current content of the new location:[2]:42[13]

move a to b ; Mem[b] := Mem[a] (+, -, *, /, …) Mem[b]

sometimes written as:

a -> b ; Mem[b] := Mem[a] (+, -, *, /, …) Mem[b]

The operation performed is defined by the destination memory cell. Some cells are specialized in addition, some other in multiplication, etc. So memory cells are not simple store but coupled with an arithmetic logic unit (ALU) setup to perform only one sort of operation with the current value of the cell. Some of the cells are control flow instructions to alter the program execution with jumps, conditional execution, subroutines, if-then-else, for-loop, etc…

A commercial transport triggered architecture microcontroller has been produced called MAXQ, which hides the apparent inconvenience of an OISC by using a “transfer map” that represents all possible destinations for the move instructions.[14]

Cryptoleq

Cryptoleq[15] is a language consisting of one instruction, the eponymous, is capable of performing general-purpose computation on encrypted programs and is a close relative to Subleq. Cryptoleq works on continuous cells of memory using direct and indirect addressing, and performs two operations O1 and O2 on three values A, B, and C:

Cryptoleq a, b, c      [b] = O1([a],[b]) ;

IP = c,  if O2[b] ≤ 0

IP = IP + 3, otherwise

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